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Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JPS57133587
Kind Code:
A
Abstract:

PURPOSE: To shorten the time of word line driving to reduce the access time, by driving word lines, where the characteristic impedance is lessened with division, by a semiconductor inversion amplifying circuit of a high driving power.

CONSTITUTION: A word line W is divided in the row direction into N-number word lines, and (N-1)-number semiconductor inversion amplifying circuits are used in every one row, and the nth (1≤n≤N-1) out of N-number divided word lines is connected to the input terminal of the nth semiconductor inversion amplifying circuit. The (n+1)th word line is connected to the outpt terminal of the nth semiconductor inversion amplifying circuit, and one or plural first cells are connected to odd-numbered (even-numbered) word lines out of N-number divided word lines, and one or plural second cells are connected to even-numbered (odd- numbered) word lines. An N channel field effect transistor TR is used as a cell selecting TR in the first cell, and a P channel field effect TR is used as a cell selecting TR in the second cell.


Inventors:
BABA TATSUO
MANO TSUNEO
SAWADA HIROTOSHI
Application Number:
JP1803081A
Publication Date:
August 18, 1982
Filing Date:
February 12, 1981
Export Citation:
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Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
G11C11/418; G11C11/414; (IPC1-7): G11C11/34



 
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