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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY AND ITS MANUFACTURING PROCESS
Document Type and Number:
Japanese Patent JPS5649570
Kind Code:
A
Abstract:

PURPOSE: To get a small-sizedmemory unit with a good holding characteristic by piling Si3N4 or polysilicon film on SiO2 film.

CONSTITUTION: Field film oxide 11, P+ channel stopper 11A are formed on a P type Si substrate 10, a polysilicon floating gate 13 layer is made on gate film oxide 12 to be covered with film oxide 14 further laminated with a polysilicon control gate 15 layer to form gate electrodes 15, 13 by single photographic etching. Next N+ source, drain 16, 17 and a source taking out layer 16' are formed through ion injection and self-matching to make polysilicon 15, 13 conductive. Nextby selectively making an opening Al bit wiring 21 connecting with an N+ layer 17 is made. By piling Si3N4 19 with the damp-proof properties on SiO2 18 covering memory cells the gate 13 has an extremely good holding characteristic and the single photographic etching makes it possible to reduce the cell size.


Inventors:
KOMORI KAZUHIRO
Application Number:
JP12412779A
Publication Date:
May 06, 1981
Filing Date:
September 28, 1979
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/8247; G11C16/04; H01L23/532; H01L29/78; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; H01L27/10
Domestic Patent References:
JPS5457972A1979-05-10