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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY AND MEMORY MIXED LOGIC LSI
Document Type and Number:
Japanese Patent JP2002260400
Kind Code:
A
Abstract:

To output data from a memory-macro even in the outside of an address space of a memory-macro at testing of a memory-macro.

A memory-macro 10 is composed of a memory cell array 11 storing data, an expected value generating circuit 12 generating a test expected value, an address detecting circuit 13 discriminating whether an external address exists in constitution of the memory-macro 10 or not and outputting a control signal (expected value output command), and a multiplexer 14 (output selecting circuit) selecting either of output data of the memory cell 11 or the expected value generating circuit 12 and outputting as data of the memory-macro 10. The expected value generating circuit 12 generates an expected value when the outside of an address space of the memory cell array 11 is accessed.


Inventors:
FUKUDA MAKOTO
Application Number:
JP2001053686A
Publication Date:
September 13, 2002
Filing Date:
February 28, 2001
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C29/00; G11C29/02; G11C29/12; G01R31/28; (IPC1-7): G11C29/00; G01R31/28
Attorney, Agent or Firm:
Togawa Hideaki