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Title:
SEMICONDUCTOR MEMORY STORAGE
Document Type and Number:
Japanese Patent JPS5848967
Kind Code:
A
Abstract:

PURPOSE: To fine an EPROM while obtaining the memory storage having an excellent information holding characteristic by isolating a section between a stacked gate and a reverse conduction type region while being made run parallel with the surface of a substrate and disposing the third opposite electrode into a region held by the gate and the region through the third insulating film.

CONSTITUTION: A thick field oxide film 2 using a P+ type channel stopper region 9 as an underlay is formed to the peripheral section of the P type Si substrate 1, the N+ type region 4 is shaped into the region A of the substrate 1 surrounded by the film 2 through diffusion while being brought close to one oxide film 2 side, and the surface layer of the substrate 1 positioned between the region 4 and another oxide film 2 is divided into the first region 13 and the second region 13' and used. That is, a floating gate 6 surrounded by SiO2 films 5, 7 and a control gate 8 are buried onto the region 13 and employed as the stacked gates, and the third electrode 15 buried into the SiO2 film 14 is shaped similarly onto the region 13' adjacent to the stacked gates, and extended up to an edge section on the gate 8. Accordingly, information is written and erased by using a tunnel effect.


Inventors:
TAKEI AKIRA
HIGA YOSHIHIKO
MITSUIDA TAKASHI
Application Number:
JP14808081A
Publication Date:
March 23, 1983
Filing Date:
September 18, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C17/00; G11C16/04; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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