To prevent the erroneous operation of a semiconductor memory by reducing power source noise.

A column memory block group includes memory blocks arrayed in a vertical direction. A row memory block group includes memory blocks arrayed in a horizontal direction. A first row address decoder activates one of a plurality of first decoding signals corresponding to a first row address. A plurality of amplifier circuits connected to a common power line corresponding to each row memory block group receive first decoding signals different from one another. Since power is supplied to the simultaneously operated amplifier circuits, a drop in power supply voltage is reduced, and power supply noise generated in the power line is reduced. Thus, the erroneous operation of the semiconductor memory is prevented. Since the number of power lines arranged in the amplifier circuits is reduced, the margin of the layout of the power lines is increased.