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Title:
SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JPH04113587
Kind Code:
A
Abstract:

PURPOSE: To reduce an occupancy area and to improve reliability by inputting and outputting storage data through a diode between an inside node connected to a word line through a cross-coupled drive FET and a bit line.

CONSTITUTION: This is constituted by a pair of FETs (a field-effect transistor) N1 and N2, which are cross-coupled and connected between word lines WL and -WL and inside nodes ND1 and ND2, a pair of diodes D1 and D2 connected between the inside nodes ND1 and ND2 and bit lines BL and -BL, and loading circuits L1 and L2 connected between the inside nodes ND1 and ND2 and a voltage source VHH. That is, the FETs N1 and N2 are the MOS type FET of N channel, and the anode sides of the diodes D1 and D2 are connected to the bit lines and the cathode sides are connected to the inside nodes. The input/output of the storage data is operated between the inside nodes ND1 and ND2 and the bit lines BL and -BL through the diodes D1 and D2. Thus, without damaging stability, it is possible to reduce the occupancy area and to improve the reliability, and a semiconductor memory suitable for making large capacity can be obtained.


Inventors:
NOGAMI KAZUTAKA
Application Number:
JP23241590A
Publication Date:
April 15, 1992
Filing Date:
September 04, 1990
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G11C11/412; (IPC1-7): G11C11/412
Domestic Patent References:
JPH02193395A1990-07-31
Attorney, Agent or Firm:
Hidekazu Miyoshi (1 outside)



 
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