PURPOSE: To prevent the generation of disconnection of an Al wiring as well as to enable to reduce the memory cell area of the titled semiconductor memory by a method wherein the first semiconductor layer part (in thickness direction) located between a semiconductor substrate and an impurity region is used as the load element of high resistance, and the semiconductor substrate is connected to a VDD power source.

CONSTITUTION: After a field oxide film 26 has been formed on a P type semiconductor layer 24 using a selective oxidization method, a gate oxide film 25 is formed on the surface of the islandlike P type semiconductor layer 24 region which is isolated by the field oxide film 26. Then, after resist has been applied on the whole surface, a resist pattern 37 is formed by performing exposure and developing processes, and a deep n type ion implantation layer 381 (382) is formed for the purpose of connecting a drain region (n+ layer) and an n type semiconductor layer. A shallow n type ion-implantation layer 40 is formed by ion implanting n type impurities in the p type semiconductor layer 24 using the field oxide film 26 and gate electrodes 27 (272) and 29 as masks, and then a thermo-annealing is performed.