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Title:
SEMICONDUCTOR NONVOLATILE MEMORY
Document Type and Number:
Japanese Patent JPS5543862
Kind Code:
A
Abstract:

PURPOSE: To carry out information write to a gate layer at a drain junction and also to carry out information erase from the gate layer at a source junction by providing an adjacency to the channel area of a control gate layer nearly intermediately between source and drain.

CONSTITUTION: A floating gate layer 16 is provided over a channel area 11 with an aperture 16A given on its center, and a part 28A of a control gate layer 28 is arranged so as to come in the aperture 16A. There is arranged a switching FETQs nearly intermediately between source and drain, which is equivalent to the case where a floating FETQf is arranged on both sides thereof. Thus information write can be carried out at the drain junction and information erase can also be carried out at the source junction.


Inventors:
KOMORI KAZUHIRO
Application Number:
JP11655078A
Publication Date:
March 27, 1980
Filing Date:
September 25, 1978
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L27/112; G11C16/04; G11C17/00; H01L21/8246; H01L21/8247; H01L29/788; H01L29/792; (IPC1-7): G11C11/40; H01L27/10; H01L29/78
Domestic Patent References:
JPS5177184A1976-07-03



 
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