To provide a semiconductor storage device configured to reduce data read time.
An input/output control circuit 20 is formed along one side of a memory cell array 17 disposed between a data input pad 11 and a data output pad 14. Further, the input/output control circuit 20 is disposed between a hold command input pad 13 and a clock input pad 16. Accordingly, it is possible to minimize the distances of wirings 21-2 and 21-4 from the input/output control circuit 20 to the pads 13 and 16 and to make the distances of the wirings 21-2 and 21-4 equal and thus to minimize the read time of the memory cell array 17. In addition, since it is also possible to make equal wiring distances from the input/output control circuit 20 to an address decoder 18 and an output multiplexer 19, it is possible to minimize the read time from the memory cell array 17.
| JPH11274424A | 1999-10-08 | |||
| JP2008165917A | 2008-07-17 | |||
| JPH04228179A | 1992-08-18 | |||
| JPH0340291A | 1991-02-21 | |||
| JPS6380546A | 1988-04-11 | |||
| JPH03205687A | 1991-09-09 |
Aniya Setsuo
Toru Yui
Hitoshi Kiyono
Fukuoka Masahiro