Title:
半導体構造及びその製造方法
Document Type and Number:
Japanese Patent JP7411826
Kind Code:
B2
Abstract:
Disclosed are a semiconductor structure and a preparation method therefor. The semiconductor structure (100) comprises: a functional structure (11) and a first mark structure (121), which are located on a substrate (10), a feature size of the functional structure (11) being the same as a feature size of the first mark structure (121); and a first dielectric layer (20), which is located at the functional structure (11) and the first mark structure (121 ), the thickness of the first dielectric layer at the functional structure (11) being different from the thickness of the first dielectric layer at the first mark structure (121).
Inventors:
Xia Yunsheng
Huang Zhen-Chou
Huang Zhen-Chou
Application Number:
JP2022558353A
Publication Date:
January 11, 2024
Filing Date:
March 09, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECHNOLOGIES,INC.
International Classes:
G03F9/00
Domestic Patent References:
| JP60229334A |
Foreign References:
| US6303460 |
Attorney, Agent or Firm:
Masao Sekiguchi