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Patent Searching and Data


Title:
SEMICONDUCTOR WAFER TESTER
Document Type and Number:
Japanese Patent JPH0287643
Kind Code:
A
Abstract:

PURPOSE: To simplify a test program and to shorten the test time by a method wherein one probe card is brought simultaneously into contact with both chips of a chip pair composed of an IC chip and a monitor chip and these chips are tested simultaneously by using one test program describing a test content of both chips.

CONSTITUTION: Discrimination resistances R, r are omitted on a wafer 1; a different function is added to the inside of chips between pads 4a, 4b and 4A, 4B. A probe card 6 contains probes 7 which simultaneously come into contact with all pads of a chip pair 5ij composed of an IC chip 2ij and a monitor chip 3ij. A program stored in advance in a test part connected to the probe card 6 is set in such a way that both the IC chip 2ij and the monitor chip 3ij are tested. When the semiconductor wafer 1 is tested, the monitor chip 3ij is first tested, a monitor characteristic data which is different from that of the IC chip 2ij is collected, and after that the IC chip 2ij is tested. When this is a bad chip, it is marked by using an inker and the probe card 6 is then shifted to a lower chip pair.


Inventors:
KOBAYASHI KAZUYUKI
Application Number:
JP24143688A
Publication Date:
March 28, 1990
Filing Date:
September 26, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/66; G01R31/26; (IPC1-7): G01R31/26; H01L21/66
Attorney, Agent or Firm:
Shin Uchihara