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Title:
SENSE AMPLIFIER CIRCUIT
Document Type and Number:
Japanese Patent JPS58114391
Kind Code:
A
Abstract:

PURPOSE: To perform the writing and reading only through a single side of a sense amplifier and to save the power consumption, by forming an FF with a cross connection of FETs and having a series connection between the FET and a potential holding circuit in which the FET is connected to a node of one side and the state of the FF is inverted at the other node.

CONSTITUTION: An FF42 is formed at a sense amplifier circuit 41 with FETQ11 and Q12 which are connected with cross at a pair of nodes M1 and M2. An FETQ13 is inserted between the node M1 and a bit line B11; while an FETQ14 and a QETQ15 forming a potential holding circuit are connected in series between the node M2 and a bit line B21. The FETQ14 hold the potential at the node M2 at a level which is needed to invert the state of the FF42 for a prescribed period in a data writing period. The data read by the circuit 41 is delivered through a main amplifier 46. In such a way, the reading, rewriting and writing are possible only through the signal side of the sense amplifier. Thus the writing can be performed without using special electric power.


Inventors:
IKEDA HIROAKI
Application Number:
JP21526981A
Publication Date:
July 07, 1983
Filing Date:
December 25, 1981
Export Citation:
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Assignee:
NIPPON ELECTRIC CO
International Classes:
G11C11/419; G11C11/409; G11C11/4091; G11C11/4096; G11C11/4097; (IPC1-7): G11C7/06; G11C11/34
Attorney, Agent or Firm:
Shin Uchihara



 
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