Title:
SENSE CIRCUIT
Document Type and Number:
Japanese Patent JP3672384
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To control generation of power source noise due to sense operations in a memory circuit.
SOLUTION: A minute potential difference is generated between a bit line pair BL, BLB by the access to, for example, a memory cell M1 in a memory array 20, and a sense circuit 30 starts a sense operation when a sense starting signal SLNGB becomes 'L'. An inverter 37 gives a signal SLNG of 'H' to the gate of an NMOS 35 and an inverter 38 gives a signal SLPG of 'L' to the gate of a PMOS 36. By this, the sense amplifiers 33, 34 are activated and a large potential difference appears between the bit line pair BL, BLB. In this case, the 'L' level of the signal SLPG outputted by the inverter 38 is an intermediate potential of the power source potentials VCC, VSS, and the on-resistance of the PMOS 36 increases compared with the case when the power source potential VSS is inputted into the gate. Namely the potential drop at the PMOS 36 increases and power noise decreases.
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Inventors:
Junichi Suyama
Fukudome Kasei
Hiro Akihiro Ta
Fukudome Kasei
Hiro Akihiro Ta
Application Number:
JP19500496A
Publication Date:
July 20, 2005
Filing Date:
July 24, 1996
Export Citation:
Assignee:
Oki Electric Industry Co., Ltd.
International Classes:
G11C11/409; G11C7/06; G11C11/401; G11C11/407; G11C11/4091; (IPC1-7): G11C11/409
Domestic Patent References:
| JP6162779A | ||||
| JP3059877A | ||||
| JP3269896A | ||||
| JP3296895A |
Attorney, Agent or Firm:
Kakimoto Yasunari