Title:
Separated CMOS and bipolar transistors, separate structures for them, and how to make them
Document Type and Number:
Japanese Patent JP6349337
Kind Code:
B2
Abstract:
Isolated CMOS transistors formed in a P-type semiconductor substrate include an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains a P-channel MOSFET in an N-well and an N-channel MOSFET in a P-well. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.
Inventors:
Disney, Donald Earl
Richard Kay, Williams
Richard Kay, Williams
Application Number:
JP2016058232A
Publication Date:
June 27, 2018
Filing Date:
March 23, 2016
Export Citation:
Assignee:
ADVANCED ANALOGIC TECHNOLOGIES INCORPORATED
International Classes:
H01L21/76; H01L21/265; H01L21/331; H01L21/336; H01L21/8228; H01L21/8248; H01L21/8249; H01L27/06; H01L27/082; H01L27/088; H01L29/732; H01L29/78
Domestic Patent References:
| JP2007523481A | ||||
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Foreign References:
| US20050179111 | ||||
| WO2007142969A1 | ||||
| US6657262 |
Attorney, Agent or Firm:
Fukami patent office