Title:
SEQUENCE CONTROLLER
Document Type and Number:
Japanese Patent JPS5962914
Kind Code:
A
Abstract:
PURPOSE:To transmit an alarm at a failure of a current device and to switch automatically the failed device to a spare device, by detecting the failure based on a residence time of each step, in a system providing the current device and the spare device in each step unit. CONSTITUTION:A memory 4 connected to a CPU1 is provided with a processing program 41, input set 42, output set 43, maximum time set 44, step number work area 45, and residence time work area 46. Further, operating end signals 51-53 relating to each step from an input I/O5 are inputted and start request signals 61-66 to each device to be controlled and an alarm output are led to an alarm circuit 7 from an output I/O6. Further, the residence time 46 is counted by a timer clock 3. Then, the residence time 46 and the maximum set time 44 are compared and when they are coincident with each other, it is discriminated as a failure. Thus, the alarm is given at a failure of the current device and the device is switched automatically to the spare device.
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Inventors:
OOHARA NAOKI
KIMURA HARUHIRO
KIMURA HARUHIRO
Application Number:
JP17260882A
Publication Date:
April 10, 1984
Filing Date:
October 01, 1982
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G05B9/03; G05B19/048; G05B19/05; G05B23/02; (IPC1-7): G05B9/03; G05B19/02; G05B23/02
Attorney, Agent or Firm:
Uchihara Shin