To prevent burden to a CPU or processing program and to enable even a processing circuit, in which the CPU does not exist, to detect abnormality in serial data transfer.

This system is provided with first and second processing circuits 100 and 200 respectively having receiving means 120 and 220 and transmitting means 110 and 220 as serial data transfer means. In this case, when performing data transfer between the transmitting means 110 of the first processing circuit 100 and the receiving means 220 of the second processing circuit 200 and between the transmitting means 210 of the second processing circuit 200 and the receiving means, 120 of the first processing circuit 100, test data transmitted from one processing circuit to be a test mode transmission side are turned with the other processing circuit to be a test mode receiving side, circulated through all signal lines and returned to one processing circuit to be the test mode transmitting side later. Thus, concerning the presence/absence of abnormality on the signal line, abnormality can be automatically detected while maintaining the direction of input/output on the signal line at the time of ordinary operation without increasing the number of signal lines or number of parts and without increasing the load of the CPU or processing program.