PURPOSE: To execute serial-parallel conversion of optional bit length, and to econimically repair a device when it is faulty, by providing a serial-parallel converting unit element of 1 bit portion in accordance with each parallel output bit, and constituting it by cascade connection.

CONSTITUTION: When a clock pulse (cp) and a selective strobe pulse (sp) are applied simultaneously to a clock signal input terminal CLIN and a selective strobe signal input terminal SBIN, a flip-flop FF1 is started by an output of an AND circuit AND1, a data on a data line lD by its timing is set to the flip-flop FF1. The clock pulse (cp) is also applied to a clock terminal C of a flip-flop FF2, the selective strobe signal is set to the flip-flop FF2, its output Q is set to "1", and this flip-flop FF2 delays the strobe pulse (sp) by clock period and sends it out to a serial-parallel converting unit element of the next stage.