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Title:
SHIFT REGISTER CIRCUIT
Document Type and Number:
Japanese Patent JPS62183099
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of elements, and to obtain an inexpensive circuit being suitable for an electronic circuit for which high function is not required, by constituting a shift direction instructing circuit, of two pieces of transfer gates per one stage of a data latch.

CONSTITUTION: When a clock control signal CLK of a high level is applied to a clock circuit 10, a complementary shift clock is outputted from the circuit 10, and inputted to a clock input terminal C, and an inversion C of data latches 1W3. However, as for the latch 2, an opposite phase input and a positive phase input are applied to the terminal C, and the terminal inversion C, respectively. When a direction instructing signal UP is inputted to the first transfer gates 4, 5 and 6, a high level signal is shifted to the next stage at every half clock portion. On the other hand, at the time of a signal inversion UP is applied to the second transfer gates 7, 8 and 9, the high level signal is shifted in the reverse direction. According to this constitution, the number of elements is decreased, and an inexpensive circuit is obtained.


Inventors:
MARUYAMA YUICHI
Application Number:
JP2533586A
Publication Date:
August 11, 1987
Filing Date:
February 06, 1986
Export Citation:
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Assignee:
NIPPON ELECTRIC IC MICROCOMPUT
International Classes:
G11C19/28; (IPC1-7): G11C19/28
Attorney, Agent or Firm:
Uchihara Shin



 
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