PURPOSE: To realize a shift register capable of lowering the driving frequencies of a driving circuit.

CONSTITUTION: Respective unit shift registers SRi of a shift register SR have three systems of delay circuits DCA to DCC connected to the output side of a sampling pulse SP 1. The output lines of the unit shift registers SRi are connected to a gate of a sampling transistor ST 1 and the output lines of the three delay circuits DCA to DCC are connected to the gates of sampling transistors ST2 to ST4. The respective delay circuits DCA to DCC form sampling pulses SP2 to SP4 shifted in phases by 1/4 frequency each of the shift clocks of the shift register SR from the sampling pulse SP 1 and supply these pulses to the respective sampling transistors ST2 to ST4.