Title:
ＳｉＣ−ＳＯＩデバイスおよびその製造方法
Document Type and Number:
Japanese Patent JP6968042
Kind Code:
B2
Abstract:
The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an n− type drift region and not penetrating a SiC substrate; an n+ type side surface diffusion region formed on each side surface of the first trench; an n+ type bottom diffusion region formed under the n− type drift region and in contact with the n+ type side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the n− type drift region at regular spacings of 0.4 μm or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.
Inventors:
Hajime Akiyama
Manabu Yoshino
Manabu Yoshino
Application Number:
JP2018134022A
Publication Date:
November 17, 2021
Filing Date:
July 17, 2018
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L29/872; H01L29/06; H01L29/47; H01L29/786
Domestic Patent References:
| JP2008085190A | ||||
| JP2008530776A | ||||
| JP11297815A | ||||
| JP2005531127A | ||||
| JP2016096165A | ||||
| JP2010157582A |
Foreign References:
| US20100033059 | ||||
| US20170323970 | ||||
| US20140061731 | ||||
| US20040067625 |
Attorney, Agent or Firm:
Yoshitake Hidetoshi
Takahiro Arita
Takahiro Arita