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Patent Searching and Data


Title:
SIGNAL AMPLITUDE ATTENUATION PREVENTING METHOD FOR CLOCK SIGNAL TRANSMISSION LINE
Document Type and Number:
Japanese Patent JPH06314913
Kind Code:
A
Abstract:

PURPOSE: To easily prevent the attenuation of an amplitude of a ultrahigh frequency clock signal on a printed circuit board.

CONSTITUTION: Plural clock signal transmission lines 2, 4 whose surge impedance differs are connected in series on an insulation board 3, a supply source 1 for an original clock signal is provided in a direction that amplification due to mismatching of positive reflection wave is implemented at adjacent connecting points of the signal transmission lines, a larger amplitude clock signal than the amplitude of the original clock signal is obtained at the signal transmission line, the clock signal after amplification is extracted from the signal transmission line to be used for the clock signal for an integrated circuit.


Inventors:
NAKAGAWA YASUHIRO
Application Number:
JP10443893A
Publication Date:
November 08, 1994
Filing Date:
April 30, 1993
Export Citation:
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Assignee:
ASIA ELECTRONICS
International Classes:
H01P5/02; H01P5/00; H03K19/0175; H05K1/02; (IPC1-7): H01P5/02; H03K19/0175
Attorney, Agent or Firm:
Takehiko Suzue