PURPOSE: To obtain a time series signal at a same speed as that of a conventional circuit even when a low speed multiplexer at a pre-stage is employed by deviating sequentially each changeover timing of plural multiplexers of the pre-stage and using a multiplexer of a post-stage so as to select an output of a multiplexer of the pre-stage just before the multiplexer is changed over.

CONSTITUTION: Each changeover timing of multiplexers 101, 102,... of the pre- stage is sequentially deviated and a changeover timing of a multiplexer 11 of a post-stage is set so that the multiplexer 11 selects an output of a multiplexer of the pre-stage among the multiplexers 101, 102,... of the pre-stage just before the changeover timing of the multiplexers 101, 102,... of the pre-stage. Thus, even when the operating speed of the multiplexers 101, 102,... of the pre- stage is slow and there is any delay time, since the output of the multiplexers 101, 102,... of the pre-stage is selected by the multiplexer 11 of the post-stage when the effect of the delay time is ineffective, low speed components are employed for the multiplexers 101, 102,... of the pre-stage and the output circuit is formed inexpensively.