Title:
SIGNAL LEAKAGE CHECK CIRCUIT FOR FPGA/PLD
Document Type and Number:
Japanese Patent JP3237584
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a diagnostic circuit which can detect interface failure with external FPGA(field programmable gate array) /PLD(programmable logic array).
SOLUTION: The signal leakage check circuit comprises a section 5 for controlling a diagnostic circuit internally, a signal generator section 3 for delivering an interface part signal of external FPGA/PLD, a diagnostic failure deciding section, a gate control section for disconnecting a program configuring circuit 2 (a circuit configured by a program user), an on chip failure informing LED, and a test pattern generating section for storing the external wiring information and pin assign information of the FPGA/PLD. The diagnostic circuit is previously embedded in a device at the fabrication stage of the device.
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Inventors:
Osamu Shiraishi
Application Number:
JP23535497A
Publication Date:
December 10, 2001
Filing Date:
August 15, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F11/22; H01L21/822; H01L27/04; H03K19/00; G01R31/28; (IPC1-7): G01R31/28; G06F11/22; H01L21/822; H01L27/04; H03K19/00
Domestic Patent References:
| JP9304485A | ||||
| JP980120A | ||||
| JP6186302A | ||||
| JP1237472A | ||||
| JP62108166A |
Attorney, Agent or Firm:
Asamichi Kato