PURPOSE: To obtain a small sized and economical circuit by constituting the circuit of a flip-flop set by an overflow signal of a counter and reset by a 2nd input signal, and of a logic circuit receiving a periodic signal and a flip-flop output, and outputting the output of the logic circuit to an external terminal.
CONSTITUTION: An abnormal operation output of a microcomputer 1 is detected by a comparator circuit 2 and a reset signal 9 resets a CPU 3 of the microcomputer 1. A signal selecting circuit 7 is a circuit outputting whether a clock signal or a watchdog timer interrupt request signal WDTO from an output terminal OUT 1. Moreover, a set/reset flip-flop(FF) 10 uses an OVF signal and a RESET signal respectively as a set and a reset signal, outputs a watchdog timer interrupt request signal WDTO, an AND gate 11 ANDs the clock signal and the WDTO and outputs a comparison signal to the external output terminal OUT 1 when they are coincident.
JPS63102416 | METHOD FOR SETTING TIME OF TIMER |
JPH04128432 | [Title of the device] Power-on-reset circuit |
JP2005110366 | DRIVE CIRCUIT |
MATSUSHIMA OSAMU
JPS5957033U | 1984-04-13 | |||
JPS6037932U | 1985-03-15 |