Title:
信号処理装置
Document Type and Number:
Japanese Patent JP5103816
Kind Code:
B2
Abstract:
A first AD converter subjects an analog signal to AD conversion by a first AD clock, and a second AD converter subjects the same analog signal to AD conversion by a second AD clock that is shifted in phase from the first AD clock by half cycle. FF circuits store the AD conversion results of the first AD converter and the second AD converter by the first AD clock and the second AD clock, respectively. FF circuits store the data of the FF circuits by the first AD clock, separately. A DPRAM writes the respective data that are stored by the FF circuits by the first AD clock as a group of data, divides the group of written data into the respective data, and reads the respective data by a logic clock in twice to output the data to an integration circuit.
Inventors:
Mitsuo Nakamura
Application Number:
JP2006205301A
Publication Date:
December 19, 2012
Filing Date:
July 27, 2006
Export Citation:
Assignee:
株式会社デンソー
International Classes:
G01S7/292; G01S17/931; G01S13/10; G01S13/42; G01S7/486
Domestic Patent References:
| JP943343A | ||||
| JP59035166A | ||||
| JP3205582A | ||||
| JP9033653A | ||||
| JP2003102729A | ||||
| JP9073769A | ||||
| JP7072237A | ||||
| JP2002094584A | ||||
| JP2005257405A | ||||
| JP2006129497A | ||||
| JP200412967A | ||||
| JP200214123A |
Attorney, Agent or Firm:
Kazuyuki Yahagi
Taihei Nonobe
Taihei Nonobe
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