Title:
SIGNAL SCRAMBLER AND CIPHERING DEVICE
Document Type and Number:
Japanese Patent JPH0575596
Kind Code:
A
Abstract:
PURPOSE: To obtain a ciphering device for secret communication which is capable of processing of plural ciphering algorithms.
CONSTITUTION: Left and right halves of an input signal are inputted to registers 97 and 98 respectively. A signal scrambler 96 repeatedly scrambles a ciphering key and the output of the register 98 at each time of input of a clock pulse. When a preliminarily set number of clock pulses are inputted, a pulse control circuit 99 sends an update signal to registers 97 and 98 to rewrite contents of registers 97 and 98. This operation is performed as the processing in one stage, and the number of pulses in each stage is independently set.
Inventors:
KATSUTA NOBORU
IBARAKI SUSUMU
NAKAMURA SEIJI
MURAKAMI HIRONORI
IBARAKI SUSUMU
NAKAMURA SEIJI
MURAKAMI HIRONORI
Application Number:
JP23014791A
Publication Date:
March 26, 1993
Filing Date:
September 10, 1991
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G09C1/00; H04L9/06; H04L9/10; H04L9/14; (IPC1-7): G09C1/00; H04L9/06; H04L9/14
Attorney, Agent or Firm:
Akira Kobiji (2 outside)