Title:
SIMULATION DEVICE
Document Type and Number:
Japanese Patent JP2788820
Kind Code:
B2
Abstract:
PURPOSE: To obtain a simulation device capable of different timing error verification or test rule error verification for each element.
CONSTITUTION: A timing error verification means 9a within a timing check primitive 9 graspes the input and output signal change of an element obtained from the signal change of a signal line between elements from the simulation execution state of a simulation execution control means 6 and performs the timing error verification having independent contents for each element based on the contents of a timing check value definition file 7. Accordingly, the timing error verification can be performed in deferent timing for each element. By performing the test rule error verification based on the contents of a test rule check value definition file in a similar manner, the different test rule error verification can be performed for each element.
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Inventors:
FUKUI YOSHIAKI
YOSHIDA NOBURO
KISHIMOTO YASUNORI
INOE YOSHIO
YOSHIDA NOBURO
KISHIMOTO YASUNORI
INOE YOSHIO
Application Number:
JP10425192A
Publication Date:
August 20, 1998
Filing Date:
April 23, 1992
Export Citation:
Assignee:
MITSUBISHI DENKI KK
International Classes:
G06F11/25; G01R31/3183; G06F17/50; G01R31/30; (IPC1-7): G06F17/50
Domestic Patent References:
| JP322038A | ||||
| JP2252066A |
Attorney, Agent or Firm:
Shigeaki Yoshida (2 outside)