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Patent Searching and Data


Title:
SIMULATION METHOD FOR LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JPS61248142
Kind Code:
A
Abstract:

PURPOSE: To reduce the quantity of necessary memory by providing the signal value storing table of 1 bit per one signal for a read only memory section etc. and providing the signal value storing table of plural bits per one signal for other parts.

CONSTITUTION: Signal storing tables 14, 15 correspond to AND gates 21, 22 and their input output signal values 105W107 are expressed by two bits per one signal. A signal value storing table 16 corresponds to a ROM 23 and an area 108 stores an input signal value, an area 109 stores an output signal value and an area 110 stores a signal value stored in the ROM. The storing table 16 allots 2 bits per one signal for an input and output signal value. However, as it is impossible for the content of memory in the area 110 except '0' and '1', it is expressed by 1 bit per one signal. Thus, 8 bits required formerly to store the signal value of 4 bits is reduced to a half, 4 bits.


Inventors:
TADA OSAMU
MIYOSHI MASAYUKI
KAZAMA YOSHIHARU
Application Number:
JP8850185A
Publication Date:
November 05, 1986
Filing Date:
April 26, 1985
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/25; G06F11/26; G06F17/50; (IPC1-7): G06F11/26; G06F15/60
Attorney, Agent or Firm:
Katsuo Ogawa