Title:
正弦波乗算回路及び正弦波乗算方法
Document Type and Number:
Japanese Patent JP4161913
Kind Code:
B2
Abstract:
A sine wave multiplication circuit multiplies an analog input signal by n (n is an integer equal to or greater than 2) weighting coefficients each having a unique value. The polarity of the analog input signal multiplied by one of the n weighting coefficients is changed over. Further, changeover among the n weighting coefficients and of the polarity is performed after every sampling period equal to ½k (k is an integer, and 2k is equal to or greater than 6 but equal to or smaller than 4n) of one period of the sine wave signal by which the analog input signal is multiplied. As a result, a staircase waveform having 2n positive and negative stairs is generated while unnecessary harmonic wave components in the proximity of the sine wave signal by which the analog input signal is multiplied can be reduced.
Inventors:
Katakura Masayuki
Application Number:
JP2004038066A
Publication Date:
October 08, 2008
Filing Date:
February 16, 2004
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06G7/161; G06G7/16; H03B19/00
Domestic Patent References:
| JP63165978A | ||||
| JP1204510A |
Attorney, Agent or Firm:
Funabashi Kuninori