Title:
SINGLE POLY ELECTRICALLY ERASABLE AND PROGRAMMABLE READ ONLY MEMORY, OR EEPROM CELL HAVING LOW IMPURITY CONCENTRATION METAL OXIDE SEMICONDUCTOR, OR MOS, CAPACITOR
Document Type and Number:
Japanese Patent JP2007073927
Kind Code:
A
Abstract:
To provide an EEPROM memory cell possible to be electrically erased and operation method for manufacturing the EEPROM by a standard CMOS process.
The present EEPROM memory cell can be manufactured by the standard CMOS process having little or no additional treatment, a single polycrystalline silicon layer is used by combining a low impurity concentration MOS capacitor, a low impurity concentration capacitor used for an EEPROM memory cell 300 can be asymmetrical in design, region is reduced by an asymmetrical capacitor, further capacitance variation caused by inversion can be also reduced by using a plurality control capacitors, and an advantage of customized tunnel course is offered when a plurality of tunnel capacitors 302 are used.
Inventors:
RIEKELS JAMES E
LUCKING THOMAS B
LARSEN BRADLEY J
GARDNER GARY R
LUCKING THOMAS B
LARSEN BRADLEY J
GARDNER GARY R
Application Number:
JP2006153676A
Publication Date:
March 22, 2007
Filing Date:
June 01, 2006
Export Citation:
Assignee:
HONEYWELL INT INC
International Classes:
H01L21/8247; H01L27/115; H01L29/788; H01L29/792
Foreign References:
| US6788574B1 | 2004-09-07 | |||
| US20030198087A1 | 2003-10-23 |
Other References:
JPN6012025314; ＲＡＳＺＫＡ Ｊ ＥＴ ＡＬ: 'Ｅｍｂｅｄｄｅｄ Ｆｌａｓｈ Ｍｅｍｏｒｙ ｆｏｒ Ｓｅｃｕｒｉｔｙ Ａｐｐｌｉｃａｔｉｏｎｓ ｉｎ ａ ０．１３muｍ ＣＭＯＳ Ｌｏｇｉｃ Ｐｒｏｃｅｓｓ' ＳＯＬＩＤ-ＳＴＡＴＥ ＣＩＲＣＵＩＴＳ ＣＯＮＦＥＲＥＮＣＥ，２００４．ＤＩＧＥＳＴ ＯＦ ＴＥＣＨＮＩＣＡＬ ＰＡＰＥＲＡ．ＩＳＳ ＣＣ．２００４ ＩＥＥＥ ＩＮＴＥＲＮＡＴＩＯＮＡＬ ＳＡＮ Ｆ , 20040215, ４６-５５, ＩＥＥＥ
Attorney, Agent or Firm:
Kazuo Shamoto
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Okimoto Kazuaki
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Okimoto Kazuaki