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Patent Searching and Data


Title:
SOLID STATE IMAGE PICK-UP ELEMENT
Document Type and Number:
Japanese Patent JPS62217656
Kind Code:
A
Abstract:

PURPOSE: To obtain a highly sensitive solid state image pick-up element, by making the impurity concentration in a P well lower than that on the side of an N-type substrate at a P-N junction part with an N+ layer, thereby effectively utilizing optical signal charge.

CONSTITUTION: On an N-type silicon substrate 1, a P well 2, N+ layers 3 and 4 and a signal line 5 are formed. The N+ layers 3 and 4 and a gate electrode 7 form an MOS transistor. The P well 2 and the layer 3 form a photodiode. The MOS transistor acts as a switching element, which reads signal charge stored in the layer 3. The P well 2 is formed as follows. At first, a P+ layer 21 is formed on the substrate 21. Then, a P-type epitaxial layer 22 is formed. Thereafter, the N+ layer 3 is formed. Electrons, which are generated in the P well, are drifted to a P-N junction part with the N+ layer 3, i.e., to the photodiode and effectively utilized as a signal.


Inventors:
SUZUKI TOSHIKI
MATSUMOTO KATSUMI
MAKI MASAHIRO
Application Number:
JP5922386A
Publication Date:
September 25, 1987
Filing Date:
March 19, 1986
Export Citation:
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Assignee:
HITACHI LTD
HITACHI DEVICE ENG
International Classes:
H01L27/146; H04N5/335; H04N5/374; (IPC1-7): H01L27/14; H04N5/335
Attorney, Agent or Firm:
Katsuo Ogawa