PURPOSE: To perform the processing in a high speed by constituting a sort processing into a private hardware which makes a pipeline processing possible.

CONSTITUTION: Element data (b) inputted to an S1 register 13 of a sort circuit 8 and element data (a) set beforehand in an S2 register 15 are compared with each other by a comparator 16. If the comparison result is (a)>(b) in case of sorting in the ascending order, data (b) is sent to an S3 register 18, and data (a) is returend to the S2 register again, and data are transposed. If the comparison result is (a)≤(b), it is judged that data (a) and (b) are arranged in the ascending order, and data (b) is sent to the S2 register 15, and data (a) is fed to the S3 register 18, and the comparator 16 leaves always larger data in the S2 register 15 and transfers smaller data to the S3 register to feed it to a vector register VR3. Consequently, when four element data in a vector register VR0 are allowed to pass the sort circuit 8, element data having a maximum value is transmitted last and is stored in a rightmost stage 10-3 of a vector register VR3.