To obtain a device which is low in power consumption and superior in linearity by providing a 3rd FET which applies a 1st level-converted control signal to the gate of a 1st FET and a 4th FET which applies a 2nd level- converted control signal to the gate of a 2nd FET.

The 3rd FET: 3 receives a logical level VH at its source, converts the level of a control signal VCNTP of positive logic, and applies the resulting signal to the gate of the 1st FET: 1. The FET: 1 receives this signal and is applied with a 1st input voltage V1 at its drain to turn on or off. The 4th FET: 4 receives the logical level VH at its source, converts the level of a control signal VCNTN of negative logic, and applies the resulting signal to the gate of the 2nd FET: 2. The FET: 2 is applied with a 2nd input voltage V2 at its source to turn on or off. To an output terminal To, the source of FET: 1 and the drain of the FET: 2 are connected.