Title:
SPEED CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS59167704
Kind Code:
A
Abstract:
PURPOSE:To make a steady speed deviation zero and to perform accurate speed control by giving such specific frequency characteristic to the amplification factor of a speed error amplifier in a speed reduction region that the amplification factor is not fixed for an optional frequency. CONSTITUTION:Such specific frequency characteristic is given to the amplification factor of the speed error amplifier in the speed reduction region so that the amplification is not fixed for an optional frequency. For example, a desired number of tracks is set to a track address counter 2 by a seek logic 1, and its output is converted to an analog signal by a D/A converter 3 and is converted to a desired target speed signal 5 through a nonlinear processing circuit 4. A differential signal between the target speed signal 5 and a current speed signal 6 which is obtained through a servo head 12, a position signal reproducing circuit 14, and a differential combining circuit 15 is amplified by a speed error amplifier 7, and the output signal is inputted to a power amplifier 8. A driving current is flowed to an actuator 10 connected to a magnetic head group 11 to accelerate it until the current speed 6 coincides with the target speed 5.
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Inventors:
ISHIZUKA HIROMI
Application Number:
JP4168783A
Publication Date:
September 21, 1984
Filing Date:
March 14, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
International Classes:
G05B11/42; G11B21/08; (IPC1-7): G05B11/42
Attorney, Agent or Firm:
Uchihara Shin