Title:
STABILIZED POWER SUPPLY CIRCUIT
Document Type and Number:
Japanese Patent JPS59191630
Kind Code:
A
Abstract:
PURPOSE:To attain the accurate power-down detection by delivering a power- down signal in response to the output of a comparator and at the same time feeding the output of the comparator back to a reference voltage generating circuit. CONSTITUTION:The output voltage V0 is divided and applied to a minus terminal of an operation amplifier A: while the reference voltage of a Zener diode ZD for reference voltage is applied to a plus terminal of the amplifier A. The amplifier A and a control transistor TR1 constitute a stabilized power supply circuit. This power supply circuit contains a TR2 which delivers a power-down signal PWD in response to the output of the amplifier A. In addition, a TR3 is provided to feed its output back to the diode ZD via a diode D in accordance with the output of the amplifier A. Thus it is possible to detect accurately a power-down state without reduction of the power supply efficiency and without affecting the power supply margin of a load circuit.
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Inventors:
FUJII TOSHIO
Application Number:
JP6567683A
Publication Date:
October 30, 1984
Filing Date:
April 15, 1983
Export Citation:
Assignee:
CASIO COMPUTER CO LTD
International Classes:
G05F1/56; G05F1/571; H03K17/22; (IPC1-7): G05F1/58; H03K17/24
Attorney, Agent or Firm:
Yasuhiko Yamada