Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
START-STOP SYNCHRONIZING SIGNAL GENERATION CIRCUIT
Document Type and Number:
Japanese Patent JPS63125029
Kind Code:
A
Abstract:

PURPOSE: To easily execute data communication even if a clock frequency and a data length are not previously set between a transmission side and a reception side by inserting a preamble bit including clock components one bit before the start bit and the stop bit of a start-stop synchronizing signal.

CONSTITUTION: A preamble bit generation means 15 is provided in a start-stop synchronizing signal generation circuit so as to insert the preamble bit including the clock components one bit before the start bit and the stop bit. Since the reception side can easily decide the clock frequency and the data length by detecting the preamble bit, the data communication can be possible even if they are not previously set on the transmission side and the reception side. Thus the communication between equipments whose data lengths are different can be easily executed.


Inventors:
YABE TOSHIHIRO
Application Number:
JP27208586A
Publication Date:
May 28, 1988
Filing Date:
November 14, 1986
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
FUJITSU LTD
International Classes:
H04L25/38; H04L7/04; H04L13/00; H04L29/06; (IPC1-7): H04L7/04; H04L13/00; H04L25/38
Attorney, Agent or Firm:
Sadaichi Igita



 
Previous Patent: JPS63125028

Next Patent: METHOD OF ACCESSING REMOTE TERMINAL