PURPOSE: To reduce the number of times of access to a required common bus in case of execution of one instruction by dividing a storage device connected to the common bud into the first storage device where instruction words are stored and which is operated at a high speed with a small capacity and the second storage device where data parts are stored and which is operated at a low speed with a large capacity.

CONSTITUTION: The storage device connected to a common bus 1 is divided into the first storage device (MEM1) 3 where instruction words are stored and which is operated at a high speed with a small capacity and the second storage device (MEM2) where data parts are stored and which is operated at a low speed with a large capacity. The first storage device (MEM1) 3 is provided with mechanisms 31 and 5, and these mechanisms transfer the read instruction word onto the common bus and analyze the instruction code, and they use the address indicated in the operand part of the instruction word to start the second storage device (MEM2) 4 where data is stored if the analyzed instruction code indicates the data transfer request from the storage device, thus constituting the system so that not only the instruction word but also the data part modified by the instruction are transferred by single instruction fetch from a central processing unit CPU 2.