Title:
記憶装置
Document Type and Number:
Japanese Patent JP7433250
Kind Code:
B2
Abstract:
A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.
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Inventors:
Shuhei Nagatsuka
Tatsuya Onuki
Takahiko Ishizu
Kiyoshi Kato
Shunpei Yamazaki
Tatsuya Onuki
Takahiko Ishizu
Kiyoshi Kato
Shunpei Yamazaki
Application Number:
JP2020568868A
Publication Date:
February 19, 2024
Filing Date:
November 22, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H10B12/00; H01L21/8234; H01L27/06; H01L27/088; H01L29/786; H10B41/70; H10B99/00
Domestic Patent References:
| JP2013065638A | ||||
| JP2016225617A | ||||
| JP2011151383A | ||||
| JP2018085507A | ||||
| JP2016225613A | ||||
| JP2018201003A |