PURPOSE: To provide a stress evaluation method and a apecimen, wherein stress analysis simulations on a micro unit structure can be precisely evaluated.

CONSTITUTION: A stress evaluation specimen S is composed of a central rectangular region 1a of a semiconductor wafer 1 and N basic structures 2 which are successively formed in a row at the same pitch on the region 1a, and the specimen S is manufactured through such a manner that a thin film prescribed in thickness (e. g. 0.2μm) is formed on all the surface of the semiconductor wafer 1, and the thin film is selectively etched to leave line patterns 3a each prescribed in width (e.g. 1μm) unremoved. The local warpage a of the unit basic structure 2 is calculated by a stress simulation, and the local warpage a is multiplied by N so as to approximately obtain the total warpage b of the stress evaluation specimen S, the actual measured warpage of the stress evaluation specimen S is compared with the total warpage b obtained by simulation to verify the accuracy of a stress simulation.