To provide a sub-rate data switch device using a bit operation function making the efficiency of a PCM channel to be maximum by allocating plural channels to one time slot through the use of a bit operation function.

When data of a sub-rate, which are inputted from a switching part 10, are bypassed and they are stored in first and second DPRAM 14-1 and 14-2 by individual channels, first and second HDLC controllers 13-l and 13-2 allocate data of the sub-rate, which are stored in second DPRAM 14-1 and 14-2, to four bits in the time slot of eight bits by individual rates. In the case of 16 Kbps, data are allocated to two bits in the time slot of eight bits. In the case of 8 Kbps, data are allocated to one bit in the time slot of eight bits. In the switching part 10, the switching operation is executed on the time slot of eight bits from a bit operation part 12 and time slot data are outputted to a desired route.