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Title:
SUBMERGED WAFER ISOLATION METHOD AND SUBMERGED WAFER ISOLATION DEVICE
Document Type and Number:
Japanese Patent JP2015233059
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a wafer isolation method capable of safely, easily, surely and promptly isolating a wafer without cracking the wafer even if the wafer is extremely thinned to the thickness of 150 μm or less, and a wafer isolation device.SOLUTION: The wafer isolation method is configured to take a wafer W1 in a top layer of a wafer stack WS out of a liquid, the wafer stack WS being formed by stacking a number of or a plurality of wafers W being immersed in the liquid. Suction surfaces of a plurality of suction pads 8a and 8b are fixed while being inclined in the same direction, the wafer W1 in the top layer is sucked by the plurality of suction pads while maintaining the inclination, and the wafer W1 in the top layer is shaped wavy, thereby forming a gap D1 between a bottom face of one end of the wafer W1 in the top layer and a top face of a neighboring lower wafer W2. A fluid is blown into the gap D1 by a fluid injection device 30 that is provided in the vicinity of edges of wafers.

Inventors:
IWAI TATSUYA
ARAI IZUMI
TSUCHIYA MASATO
Application Number:
JP2014118820A
Publication Date:
December 24, 2015
Filing Date:
June 09, 2014
Export Citation:
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Assignee:
MIMASU SEMICONDUCTOR IND CO
International Classes:
H01L21/677; B65G49/04; B65G49/07
Domestic Patent References:
JP2011124481A2011-06-23
JP2003165082A2003-06-10
JPH07228370A1995-08-29
JP2010076929A2010-04-08
Foreign References:
US20050002774A12005-01-06
Attorney, Agent or Firm:
Shinsuke Ishihara
Shoji Ishihara