Title:
SUBSTRATE PROCESSOR
Document Type and Number:
Japanese Patent JP3442686
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To secure a work area in a processing station, while the processing station is miniaturized, for example, in an application/development device.
SOLUTION: A processing station S2, for applying resist and heaping developer, is connected to a cassette station S1 to/from which a wafer cassette 22 is carried. In the station S2, a first processing unit U1 an antireflection film forming unit 3 and an application unit 4 arranged in two stages is installed on the left side as seen from the cassette station S1, a second processing unit U2 where a developing unit 4 and a peripheral edge aligner 7 are arranged in two stages, so that it faces the first processing unit U1 is installed on the right side and respective two wafer transfer means MA1, MA2, MA3 and MA4 are arranged in regions facing the row of the processing units U1 and U2. In such layout, a work area can be secured in the area between the first and second processing units U1 and U2.
Inventors:
Kazunari Ueda
Application Number:
JP15405699A
Publication Date:
September 02, 2003
Filing Date:
June 01, 1999
Export Citation:
Assignee:
東京エレクトロン株式会社
International Classes:
H01L21/306; C23F1/08; H01L21/00; H01L21/027; H01L21/30; H01L21/677; (IPC1-7): H01L21/027; H01L21/68
Domestic Patent References:
| JP1119565A | ||||
| JP10305256A | ||||
| JP6310083A | ||||
| JP77067A | ||||
| JP10163292A |
Attorney, Agent or Firm:
Toshio Inoue (1 outside)
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