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Patent Searching and Data


Title:
SUM OF PRODUCT CIRCUIT AND INCLINATION DETECTING DEVICE
Document Type and Number:
Japanese Patent JP2000222386
Kind Code:
A
Abstract:

To provide an inclination detecting device quickly calculating the inclination of an image by a small circuit.

The sum of product circuit 50 for multiplying two input voltages by a prescribed coefficient respectively, and for adding those products is provided with a νMOS type transistor constituted of a drain 70, source 72, and floating gate 74 and an output terminal for outputting a voltage generated between first and second capacitances C1 and C2 for capacitive coupling two input voltages with the floating gate 74 and a resistance element and the νMOS type transistor. In this case, a fixed voltage is applied through the resistance element between the drain 70 and the source 72. The resistance element can be provided with the νMOS type transistor. This circuit can be provided with a third capacitor for connecting the floating gate 74 with ground. The νMOS type transistor is an N channel νMOS transistor, and the drain 70 is connected with a potential higher than that of the source 72.


Inventors:
MARUO KAZUYUKI
SHIBATA SUNAO
Application Number:
JP30732199A
Publication Date:
August 11, 2000
Filing Date:
October 28, 1999
Export Citation:
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Assignee:
ADVANTEST CORP
SHIBATA SUNAO
International Classes:
G06F7/548; G06F17/10; G06G7/14; G06G7/22; G06T7/60; (IPC1-7): G06F17/10; G06G7/22
Attorney, Agent or Firm:
Ryuka Akihiro