Title:
SWITCHED CAPACITOR ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP3630796
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To decrease the number of capacitors by performing the ON/OFF control of the 1st to 7th switches and also controlling the voltage applied to the 1st and 2nd capacitors at each proper level.
SOLUTION: The 1st to 7th switch elements 30, 33, 35, 37, 38, 40 and 42 consist of n-channel MOS transistors respectively and are turned on when the timing signals &phiv 1 and -&phiv 1 applied to every gate of transistors are set at high levels. At the same time, an input terminal 43 is connected to the positive phase + input of an operational amplifier 36 and an output terminal 44 is connected to the output of the amplifier 36 respectively. In such a constitution, the necessary circuit operations are secured even with the capacitors in a number smaller than the ordinary number by one, i.e., the 1st and 2nd capacitors 32 and 39. In addition, the troubles of both occupied area and conversion accuracy can be simultaneously eliminated since it is easier to equalize the capacitance of two capacitors than of three.
Inventors:
Masaru Otsuka
Application Number:
JP25730895A
Publication Date:
March 23, 2005
Filing Date:
October 04, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
G06G7/14; G06G7/186; H03H19/00; H03M1/66; (IPC1-7): H03M1/66; G06G7/186; H03H19/00
Domestic Patent References:
| JP6342523A |
Attorney, Agent or Firm:
Gunichiro Ariga
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