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Patent Searching and Data


Title:
SYMBOL CLOCK REPRODUCING DEVICE
Document Type and Number:
Japanese Patent JPH10135922
Kind Code:
A
Abstract:

To shorten the time rate of communication interrupt and to improve quality by reducing the step-out of reproducing symbol clocks, due to the rapid degradation of a reception level and reception waveform distortion by multi-path phading.

By comparing a distribution amount, calculated over one slot length of the zero cross phase of a symbol clock component with a certain fixed threshold value in a threshold value judgement means 27, judging reception signal degradation when it is larger than that and stopping phase tracking by a digital PLL, the rapid decline of the reception level by fading and shadowing generated during communication, the waveform distortion of reception signals generated by the multi-path fading and the same channel interference by nonnegligible delay spread or transition to the step-out state of clock synchronization by the intermittent reception of a silence interval in VOX control are prevented.


Inventors:
KIMURO HIROAKI
Application Number:
JP28953896A
Publication Date:
May 22, 1998
Filing Date:
October 31, 1996
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H04L1/00; H04B7/26; H04J3/00; H04J3/06; H04L7/00; H04L7/08; (IPC1-7): H04J3/06; H04B7/26; H04J3/00; H04L1/00; H04L7/00; H04L7/08
Domestic Patent References:
JPH06252964A1994-09-09
JPH0766770A1995-03-10
Attorney, Agent or Firm:
Tomoyuki Takimoto (1 person outside)