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Patent Searching and Data


Title:
SYNAPTIC CIRCUIT
Document Type and Number:
Japanese Patent JP2002222386
Kind Code:
A
Abstract:

To provide a synaptic circuit which can easily be constituted by combination of only an NMOS transistor and a PMOS transistor being advantageous for integration and a circuit having a linear resistance value.

The drain terminal of the PMOS transistor is connected with a first circuit having a first linear resistance value and the drain terminal of the NMOS transistor is connected with a second circuit having a second linear resistance value to configure a voltage dividing circuit consisting of the series connection of the first circuit and the second circuit and having an output. The synaptic circuit is obtained by connecting each of the output terminals of a plurality of the voltage dividing circuits in common to make it a common node. The result of the arithmetic of a product sum weighted to the inputs of a first input terminal and a second input terminal of the synaptic circuit is generated at the common node. The weight is learned by varying the resistance values of the first circuit and the second circuit.


Inventors:
HAN KOKA
Application Number:
JP2001018937A
Publication Date:
August 09, 2002
Filing Date:
January 26, 2001
Export Citation:
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Assignee:
HAN KOKA
International Classes:
G06G7/60; G06N3/063; H03F3/16; (IPC1-7): G06G7/60; G06N3/063; H03F3/16
Attorney, Agent or Firm:
Noriyasu Sakamoto