Title:
シナプス回路、演算装置およびニューラルネットワーク装置
Document Type and Number:
Japanese Patent JP6926037
Kind Code:
B2
Abstract:
According to an embodiment, a synapse circuit includes: a buffer that changes an output signal to a second logical value at a timing when an input signal exceeds a first threshold level, in a case where the output signal has a first logical value in a first mode, and changes the output signal to the second logical value at a timing when the input signal exceeds a reference level lower than the first threshold level, in a case where the output signal has the first logical value in a second mode; an adjusting unit that adjusts the first threshold level depending on a stored coefficient; and a mode switching unit that operates the buffer in the first mode during a period in which an acquired spike is not generated, and operates the buffer in the second mode during a period in which the spike is generated.
Inventors:
Marugame Takao
Kumiko Nomura
Yoshifumi Nishi
Kumiko Nomura
Yoshifumi Nishi
Application Number:
JP2018140290A
Publication Date:
August 25, 2021
Filing Date:
July 26, 2018
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06N3/063; G06G7/60
Foreign References:
| US5615305 | ||||
| WO2016158691A1 |
Attorney, Agent or Firm:
Sakai International Patent Office