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Patent Searching and Data


Title:
SYNCHRONIZATION CONTROL SYSTEM OF FRAME
Document Type and Number:
Japanese Patent JPS607248
Kind Code:
A
Abstract:

PURPOSE: To attain the synchronism between a reception data and a data processing by a data at a last frame of a block by preparing a save area the same in size as the maximum length of a data block length to a command requiring a large quantity of processing time such as expanding processing of an image data and releasing a busy status when the data in the save area is lost.

CONSTITUTION: A device 3 sets a frame transmitted from a multi-controller 2 to a reception buffer 31, the data part (including order) in it is saved to a save buffer 32 and the expanding processing is started. The data is saved by the number of received frames to revise a save pointer A-PTR. In the expanding processing, on the other hand, data are extracted sequentially from a save buffer 32 according to processing pointer B-PTR to attain the expanding processing. The device 3 turns off the save flag by regarding the expanding processing for a data for one block's share as it is completed when the contents of both the save pointer A-PTR revised by data save and the processing pointer B-PTR revised by the completion of the expanding processing are concident.


Inventors:
NAGAMI SHINJI
TAKAHASHI MITSUGI
Application Number:
JP11561683A
Publication Date:
January 16, 1985
Filing Date:
June 27, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L29/02; G06F13/00; G06F13/42; H04L13/08; H04L29/10; (IPC1-7): H04L13/00; G06F13/00
Attorney, Agent or Firm:
Kyotani Shiro