Title:
SYNCHRONIZING SIGNAL DETECTING DEVICE
Document Type and Number:
Japanese Patent JP2759607
Kind Code:
B2
Abstract:
PURPOSE: To provide a synchronizing signal detecting device which can simplify the circuit constitution to allow the 1-bit error of a synchronizing signal and also can decrease the number of elements.
CONSTITUTION: The received synchronizing signal is inputted to a 1st comparator 11 and compared with a reference pattern. When the equality of comparison is confirmed, an H level is outputted. This H-level output is inputted to the 1st and 2nd priority encoders 13 and 14 so that the priority is reversed between the input terminals of both encoders 13 and 14. The output of the encoder 13 is inputted to a 2nd comparator 15, and the output of the encoder 14 is inputted to the comparator 15 via an inverter circuit 16. Meanwhile the output of the comparator 11 is also sent to an AND circuit 17, and the output of the circuit 17 and the output of the comparator 15 are inputted to an OR circuit 18. Therefore the output of the comparator 15 is equal to 1 by a 1-bit error, and the output of the circuit 17 is equal to 1 in a full-effuality state. Thus the output of an OR element is O when the synchronizing signal has two or more bits.
Inventors:
MOGI KOTA
Application Number:
JP6463294A
Publication Date:
May 28, 1998
Filing Date:
March 07, 1994
Export Citation:
Assignee:
YUPITERU KOGYO KK
International Classes:
H04L1/00; H04L7/08; (IPC1-7): H04L1/00; H04L7/08
Domestic Patent References:
| JP7143116A | ||||
| JP6155742A | ||||
| JP576919A |
Attorney, Agent or Firm:
Shinichi Matsui
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