Title:
SYNCHRONOUS CLOCK FOR GENERATING CIRCUIT
Document Type and Number:
Japanese Patent JP3635001
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To minimize a board space and to obtain a stable synchronous signal of high quality by generating a synchronous signal which marks a prescribed side edge for an internal clock having its phase matched with that of an external system clock.
SOLUTION: An external system clock is supplied to a subsystem called a 'master' 24 among plural subsystems 22. The master 24 includes a voltage- controlled oscillator(VCO), which has the frequency equal to a multiple of the external system clock and generates a VCO clock signal, having its frequency matched with that of the external system clock. An internal system clock is generated in the master 24 and has the frequency which is equal to that of the external system clock and is matched with the phase of the VCO clock signal. Then the master 24 generates a synchronous signal which marks a prescribed side edge of the internal clock signal. The VCO clock signal, which functions to secure the synchronization of all subsystems 22, is supplied to every subsystem 22 so as to make these clock signals arrive at the same phase.
Inventors:
Eric Hogle
Ulrich Fiedler
Ulrich Fiedler
Application Number:
JP2000094511A
Publication Date:
March 30, 2005
Filing Date:
March 30, 2000
Export Citation:
Assignee:
Infineon Technologies North America Corp.
International Classes:
G06F1/10; G06F1/12; H03K5/00; H03L7/06; H03L7/08; H04J3/06; H04L7/00; H04L7/033; (IPC1-7): H04L7/033; G06F1/10; G06F1/12; H04L7/00
Domestic Patent References:
| JP5244131A | ||||
| JP2000101553A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
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